1. Field of the Invention
The present invention generally relates to methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers. Certain embodiments relate to performing measurements on all wafers in at least one lot at all measurement spots on the wafers and determining parameters for a dynamic sampling scheme for the process based on results of the measurements.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a specimen such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that typically involves transferring a pattern to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to monitor and control the process. For example, metrology processes are used to measure one or more characteristics of a wafer such as a dimension (e.g., line width, thickness, etc.) of features formed on the wafer during a process such that the performance of the process can be determined from the one or more characteristics. In addition, if the one or more characteristics of the wafer are unacceptable (e.g., out of a predetermined range for the characteristic(s)), the measurements of the one or more characteristics of the wafer may be used to alter one or more parameters of the process such that additional wafers manufactured by the process have acceptable characteristic(s).
Metrology has also been used to measure stress in films deposited on semiconductor wafers. Efforts to increase die yield have been focused on minimizing the overall stress in wafers by maintaining the stress at each process step below a control limit. Various methods involving global stress measurements have been developed to monitor the overall stress. One method includes measuring the shape of the wafer before a process step and then repeating the shape measurement after the process step. If the stress and film thickness are reasonably uniform across the wafer and if the change in the shape of the wafer is not large compared with the thickness of the wafer, then Stoney's equation may be used to calculate the film stress.
There are a number of disadvantages to using metrology processes and tools to measure one or more characteristics of a wafer for process monitoring and control applications. For example, most metrology tools are relatively stow, particularly compared to inspection systems. Therefore, metrology processes are often performed at one location or a limited number of locations on the wafer such that metrology results may be acquired in a relatively expedient manner. As such, in order to provide sufficient metrology results without significantly reducing the throughput of the fabrication process, the wafers that are measured and the measurements performed on the wafers should be carefully selected. The wafers that are measured and the number of measurements performed per wafer are commonly referred to as the “sampling” of the metrology process.
In standard metrology processes, the sampling may be selected once per layer or even once per fabrication facility (or “fab”) and are not changed at all. As such, these processes are disadvantageous due to the insensitivity of the sampling to fabrication process variations and changes. In particular, the same sampling rate is used form fabrication process with low variations and a fabrication process with high variations. Therefore, some methods and systems have been developed to increase the sensitivity of the sampling of the metrology process to the variations in the fabrication process.
Examples of methods and systems for varying the sampling of a metrology process are illustrated in U.S. Pat. No. 6,442,496 to Pasadyn et al., U.S. Patent Application Publication No. 2004/0121495 by Sonderman et al., and International Publication No, WO 2004/061938 by Sonderman et al., which are incorporated by reference as if fully set forth herein. In the methods and systems described in these publications, dynamic sampling is performed when a decision to change the sampling rate is taken if the current outcome of a metrology process is different from the outcome predicted by some model. In particular, these methods and systems determine the amount of deviation between measurements on manufactured semiconductor wafers as compared to the expected results determined by a manufacturing model. If the amount of deviation is high, the methods and systems assume that the accuracy of the manufacturing process is tow, and the sampling rate is increased to acquire production data that more accurately reflects the actual results of the manufacturing process. The sampling rate is changed in this manner assuming that acquiring more production data increases the accuracy of the production data and that when the accuracy of the production data is more reflective of the actual manufacturing process results, calculations of the model errors that are used to modify control input parameters to the manufacturing tool become more precise.
The methods and systems described in these publications are, however, disadvantageous due to the use of the model. In particular, the decisions to alter the sampling rate are based upon differences between output of a model and measurement results on manufactured wafers. Therefore, if there are errors in the model, these errors will lead to oversampling or undersampling of the manufactured wafers. Oversampling and undersampling are both disadvantageous. In particular, unnecessary oversampling of the manufactured wafers can lead to lower throughput of the manufacturing process while undersampling of the wafers can result in substantially inaccurate process monitoring and control and reduced yield of the manufacturing processes.
Accordingly, it would be advantageous to develop methods and systems for creating and/or performing a dynamic sampling scheme for a process during which measurements are performed on wafers, which can be used to increase (or at least maintain) throughput of fabrication processes performed on the wafers and to increase accuracy of process monitoring and control and yield of the fabrication processes.